"Fabrication of 50nm tri-gate SOI MOSFET without source/drain activation annealing"

K. Im*, W.-j. Cho, C.-G. Ahn, Y.-H. Yang, J. Oh, and S. Lee , Japanese Journal of Applied Physics 43, 2438 (2004)

"Characteristics of solid-phase diffused ultra-shallow junction using phosphorus doped silicon oxide films for fabrication of sub-100 nm SOI MOSFET"

W.-j. Cho*, K. Im, J.-H. Yang, J. Oh, S. Lee, and K. Park , Journal of Materials Science 39, 1829 (2004)

"Defect-free ultra shallow source/drain extension using spin-on-dopants for deep submicron SOI MOSFET applications"

Y.-H. Yang*, J. Oh, W.-j. Cho, S. Lee, K. Im, and K. Park , Journal of the Korean Physics Society 44, 423 (2004)

"Characteristics of Erbium silicided n-type Schottky barrier tunnel transistor"

M. Jang*, J. Oh, K. Kang, W. Cho, S. Maeng, S. Lee, and K. Park , Applied Physics Letters 83, 2611 (2003)

"Fabrication and process simulation of SOI MOSFETs with a 30-nm gate length"

W.-j. Cho*, J.-H. Yang, K. Im, J. Oh, S. Lee, and K. Park , Journal of the Korean Physics Society 43, 897 (2003)